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Motor Drivers for Printers
System Driver for Ink Jet Printers
BD64550EFV
No.10016EAT03
Description This is 1-chip system motor driver integrating 2-channel H-bridge driver, step-down switching regulator with built-in power DMOS, series regulator and reset output. Features 1) Low-on resistance output H-bridge driver (2-channel) 2) Constant-current chopping drive H-bridge driver 3) Switching regulator with built-in P-channel power DMOS FET 4) Soft start function: 23.6 ms (Typ.) 5) Reset release timer: 80 ms (Typ.) 6) 16 bit serial interface 7) Logic input interface (serial/parallel changeable) 8) Ultra thin type high heat dissipation HTSSOP-B40 package 9) Overcurrent protection in H-bridge driver block 10) Input voltage low voltage protection in H-bridge driver block 11) Overcurrent protection in switching regulator block 12) Output overvoltage protection in switching regulator block 13) Output low voltage protection in switching regulator block 14) Thermal shutdown Applications Inkjet printer, photo printer, etc. Absolute Maximum Ratings (Ta=25) Parameter VM applied voltage Logic input voltage RIN applied voltage RNF voltage Power dissipation Operating temperature range Storage temperature range Junction temperature Motor driver output current (peak 500 ns) Motor driver output current (DC) Switching regulator output current (DC) Series regulator output current (DC) Symbol VM VL VRIN VRNF Pd TOPR TSTG Tjmax Iomax (peak) Iomax (DC) Iomax Iomax Ratings 40 -0.4 ~ 5.5 5.5 0.5 1600* -25 ~ +85 -55 ~ +150 150 8.0 2.5** 0.5 0.25 Unit V V V V mW A A A A
* Reduced by 12.8 mW/ over 25 , when mounted on a glass epoxy board (70 mm x 70 mm x 1.6 mm). ** Must not exceed Pd or ASO.
Operating Conditions Parameter VM operating power supply voltage range SCLK max. operating frequency Switching regulator output voltage range Symbol VM FSCLK Vswreg Limit 7 ~ 36 20 3~5 Unit V MHz V
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2010.06 - Rev.A
BD64550EFV
Electrical Characteristics (Unless otherwise specified,Ta=25,VM=24V) Parameter Overall VM current 1 VM current 2 H-bridge 1 Output on resistance (source side)) Output on resistance (sinking side) Output leak current Built-in diode forward direction voltage (source side) Built-in diode forward direction voltage (sinking side) H-bridge 2 Output on resistance (source side) Output on resistance (sinking side) Output leak current Built-in diode forward direction voltage (source side) Built-in diode forward direction voltage (sinking side) Current control VREF voltage range VREF pin outflow current RNF pin outflow current RNFS pin outflow current VREF-RNFS offset voltage Control logic High input voltage Low input voltage Input current Switching power source DSEN threshold voltage Output on resistance Leak current DUTY_MAX value Clock frequency DSEN pin outflow current Series power source Output voltage Leak current RESET pin Output voltage Leak current High VM threshold voltage Low VM threshold voltage High motor UVLO voltage Low motor UVLO voltage Reset delay time VRSTL IRSTLEAK VMPORH VMPORL VMMTH VMMTL TPOR 0 0 6.3 5.9 13.5 12.5 50 6.5 6.1 15 14 80 0.2 10 6.7 6.3 16.5 15.5 110 V A V V V V ms VSOUT ISLEAK 1.425 0 1.5 1.575 10 V A VSWBIAS RSWON ISWLEAK DMAX FSW IDSEN 0.873 0 130 0.9 0.8 92 200 0 0.927 1.04 10 270 1 V A % kHz A VINH VINL IIN 2.0 0 21 33 5.5 0.8 45 V V A VREF IREF IRNF IRNFS VOFFSET 0.8 5 -15 0 15 0 0 3.5 1 30 1 15 V A A A mV RONH2 RONL2 ILEAK2 VFH2 VFL2 0 0.6 0.6 0.7 0.5 0.9 0.9 0.91 0.65 10 1.2 1.2 A V V RONH1 RONL1 ILEAK1 VFH1 VFL1 0 0.6 0.6 0.6 0.4 0.9 0.9 0.78 0.52 10 1.2 1.2 A V V IVM1 IVM2 8 12 mA mA Symbol Limit Min. Typ. Max. Unit
Technical Note
Conditions
VM=7V VM=24V Io=1A Io=1A VM=36V Io=1A Io=1A
Io=1A Io=1A VM=36V Io=1A Io=1A
VREF=2V
Input voltage=3.3V
At Io=250mA VM=36V
At Io=70mA
IDRAIN=1mA VM at power on VM at power off Off motor only
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2010.06 - Rev.A
BD64550EFV
Reference Data
6 25 Circuit current :Icc[mA] 85
8.00
Technical Note
1.2
CLK8M [MHz]
4
-25
6.00
0.8 Vref [V] 0.4 0.0
-25 0 25 50 75
4.00
2
2.00
0 0 8 16 24 32 Supply voltage :VM[V]
0.00 Temperature []
-25
0
25 50 Temperature ()
75
Fig.1 VM Current
1.4 1.2 Output H voltage :VOH[V]
Fig.2 Internal Reference Clock (VM=24V)
0.9 0.8 Output L voltage :VOL[V] 85
Output H voltage :VOH[V]
Fig.3 Temperature dependence of Internal Standard Voltage (VM=24V)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 25 85
1.0 0.8 0.6 25
0.7 0.6 0.5 0.4 0.3 0.2 0.1 25
85
-25 0.4 0.2 0.0 0 400 800 1200 1600 2000 Supply current :Io[mA]
-25
0.0 0 400 800 1200 1600 Supply current :Io[mA] 2000
0
400
800
1200
1600
2000
Supply current :Io[mA]
Fig.4 OUT1 High Output Voltage (source side)
1.4 1.2 Output L voltage :VOL[V] 1.0 0.8 0.6 0.4 0.2 0.0 0 400 800 1200 1600 2000 Supply current :Io[mA] -25 25
Fig.5 OUT1 Low Output Voltage (sinking side)
500
Fig.6 OUT2 High Output Voltage (source side)
100 VM=7V
Swout voltage :Rsw[mV]
400 85 300 25 200 -25 100
80 Output effect:[%] VM=24V
85
60
40
20
0 0 100 200 300 400 500 Supply current :Io[mA]
0 0 100 200 300 400 500
Output current :[mA]
Fig.7 OUT2 Low Output Voltage (sinking side)
2.0
Fig.8 Switching Regulator High Output Voltage
4 -25 25 85
Fig.9 Switching Regulator Efficiency (Ta=25)
1.8
Swout voltage :SV[mV]
3
Rout voltage:[V]
1.6
2
1.4
1.2
1
1.0 0 50 100 150 200 250 Supply current :[mA]
0 0 2 4 6 8
Supply v oltage :VM[V]
Fig.10 Series Regulator Load Regulation (VM=24V, Ta=25)
Fig.11 Reset Output (Pull up to switching regulator at 10k)
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2010.06 - Rev.A
BD64550EFV
Block Diagram, Application Circuit Diagram, and Pin Function
Technical Note
Be sure to use VM1,VM2.VM3 and VM4 by short-circuit. VM2
32 33 8 9
VM1 VM1 OUT1P
VM2 OUT2P
39 34 7 2
Pre driver
Pre driver
OUT2M RNF2 0.2 (0.04~0.35) RNF2
37 38 36
OUT1M CONTROL LOGIC
3 4 5
0.2(0.04~0.35) Io1=(VREF1/10)(1/RNF1S) See P.9.
RNF1 RNF1 RNF1S VREF1 300F (220F~470F) 0.2 (0.04~0.35)
N.C. OUT1M RNF1 RNF1 RNF1S N.C. OUT1P VM1 VM1 VM4 N.C. SWOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
PGND OUT2P RNF2 RNF2 RNF2S N.C. OUT2M VM2 VM2 VM3 N.C. AGND RESET SCLK SDATA STROBE DC2P DC2E SELECT DGND
RNF2S VREF2 19 Same as RNF1 SELECT 22 DC2P 24 SCLK(DC1P) 27
1/10
1/10
20
31 28
VM3 RESET
Serial Selector Control
DC2E STROBE(DC1E)
23 25
POWER MONITOR
RESET
SDATA 26 AGND
29 16
40
PGND
N.C. ROUT N.C. RIN N.C. DSEN VREF2 VREF1
DGND 21 OSC UVLO TSD BG
10
From VDCDCOUT RIN ROUT
VM4
REG
14
BG BG
DRIVER
SWOUT VDCDCOUT 220H 2.7k
12
1F (0.1F~2.2F)
18
4700pF 100F DSEN 1k The figure on the left-hand side shows optimum recommended values. See P.10 for setting.
Fig.12 Block Diagram and Application Circuit Diagram No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin name NC RNF1 RNF1 RNF1S NC VM1 VM1 VM4 NC NC ROUT NC RIN NC DSEN VREF2 VREF1 Function Non Connection Output current detection pin 1 Output current detection pin 1 Output current detection input pin Non Connection Motor power supply pin Motor power supply pin Switching regulator power supply pin Non Connection Non Connection Series regulator output pin Non Connection Series regulator power supply pin Non Connection Switching regulator voltage sense pin Reference voltage input pin Reference voltage input pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
*
Fig.13 Pin Assignment Diagram Pin name DGND DC2E DC2P STROBE SDATA SCLK Function Digital GND H-bridge 2 side enable input pin H-bridge 2 side phase pin Serial port strobe input pin / H-bridge 1 side enable pin Serial port data input pin Serial port clock input pin / H-bridge 1 side phase input pin ANALOG GND Non Connection Power supply pin Motor power supply pin Motor power supply pin Non Connection Output current detection input pin Output current detection pin 2 Output current detection pin 2 POWER GND
OUT1M H-bridge output pin 1M
SELECT Input pin select pin
OUT1P H-bridge output pin 1P
RESET Reset signal output pin AGND NC VM3 VM2 VM2 NC RNF2S RNF2 RNF2 PGND
SWOUT Switching regulator output pin
OUT2M H-bridge output pin 2M
OUT2P H-bridge output pin 2P
Precaution regarding VM pin If you use VM1, VM2, VM3 and VM4 not by short-circuit, they may be destroyed. Be sure to use them by short-circuit. And be sure to set up a bypass capacitor (220F to 470F) closer to VM3 pin as much as possible.
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2010.06 - Rev.A
BD64550EFV
Technical Note
Pin selection function Either serial control or external PWM control can be selected for motor control type with SELECT pin (pin 22). SELECT Output state L H Serial input mode External PWM control mode
STROBE/DC1E(25pin)
ENA PHA
SEL OUTPUT SEL Serial
Internal shift register
SDATA(26pin)
Control Logic
SCLK/DC1P(27pin) Serial DC2P(24pin) DC2E(23pin) SELECT(22pin) Serial
SEL
SEL
Fig.14 Serial Input Block Diagram The input/output logic at SELECT = H is as follows. DC1E/DC2E L H DC1P/DC2P L H OUTP SINK SOURCE Output state Open ACTIVE OUTM SOURCE SINK
Procedure of DC motor drive by external PWM control 1) Serial setting Set the serial by SELECT pin = L. (WORD_S and WORD_D setting) WORD_S (see P.7) is a drive parameter for setting OFF_TIME, BLANK TIME etc. WORD_D (see P.7) is for drive setting to set drive mode of each H-bridge. When setting WORD_D (see P.7), make sure that ENABLE signal (ENABLE_1ENABLE_2) of serial bit is L. If ENABLE signal is H, the motor may operate. Input of DC2P pin can be either H or L. 2) External PWM drive mode switch Set external PWM drive mode by SELECT pin = H. Switch by DC1E (STROBE)/CD2E pin = L when switching SELECT pin. 3) Drive PHASE, ENABLE pin input signal (DC1E/DC1P/DC2E/DC2P) drives in external PWM mode.
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2010.06 - Rev.A
BD64550EFV
Technical Note
Serial interface 16-bit 3-linear type serial interface (SDATA (pin 26), SCLK (pin 27), STROBE (pin 25)) is provided to set the operation and the value of current limit. Data are sent to the internal shift register by falling edge of SCLK pin in the area L of STROBE pin. Data of shift register are written in an appropriate address of internal memory of 2*15 bits by rising edge of STROBE pin according to address data of D15.The input order of serial data is from D0 to D15. Address data D15 0 1 Word select WORD_S WORD_D
Memory data allocation BIT WORD_S D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 Rohm_Reserve[2] Rohm_Reserve[1] Rohm_Reserve[0] OFF TIME_2[2] OFF TIME_2[1] OFF TIME_2[0] BLANK TIME_2[1] BLANK TIME_2[0] OFF TIME_1[2] OFF TIME_1[1] OFF TIME_1[0] BLANK TIME_1[1] BLANK TIME_1[0] MASK SELECT SWOFF
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WORD_D Rohm_Reserve[11] Rohm_Reserve[10] Rohm_Reserve[9] Rohm_Reserve[8] Rohm_Reserve[7] Rohm_Reserve[6] Rohm_Reserve[5] Rohm_Reserve[4] Rohm_Reserve[3] PWM_MODE_2 S_PHASE_2 S_ENABLE_2 PWM_MODE_1 S_PHASE_1 S_ENABLE_1
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The timing of serial report writing is shown in the right figure. And the minimum timing of each is as follows: ASDATA setup time 10nsec BSDATA hold time 10nsec CSetup STROBE to SCLK falling edge 50nsec DSCLK low pulse width 25nsec ESCLK High pulse width 25nsec FSetup SCLK falling edge to STROBE 25nsec GSTROBE pulse width 50nsec HSetup RESET to SCLK Rising 50sec
H
RESET STROBE D SCLK A SDATA D0 B D1 D15 E F G C
RESET signal is an internal RESET signal and generated inside IC at the same timing of external RESET output. STROBE, SCLK and SDATA signals are input signals through external ASIC.
Fig.15 Serial Signal Input Timing
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2010.06 - Rev.A
BD64550EFV
Serial Port Explanation WORD_S SWOFF Set on/off of switching regulator circuit. 0 Switching regulator on 1 Switching regulator off
Technical Note
MASK SELECT Common mask can be provided to 2-phase H-bridge drive noise mask (BLANK time). 0 Independent mask on single-phase/two-phase. 1 Common mask on single-phase/two-phase.
BLANK TIME Current-limit comparator monitors RNF pin voltage to set limit to current, but during the period from switching on to BLANK TIME, detection becomes invalid in order to avoid wrong detection caused by spike noise that happens at the time of switching on. See P.8 for details.And during the period from ENABLE signal on to BLANK TIME at switching of PHASE signal, detection becomes invalid as well. [1] 0 0 1 1 [0] 0 1 0 1 BLANK TIME 2.0 3.0 4.0 5.0 Unit s s s s
OFF TIME Set current decay time. [2] [1] [0] 0 0 0 0 1 1 1 1 WORD_D 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
OFF TIME 6 8 10 12 14 16 18 20
Unit s s s s s s s s
S_ENABLE_1/S_ENABLE_2 Each bridge on/off signal. Output state is as follows. Output state 0 1 Open ACTIVE
S_PHASE_1/S_PHASE_2 Set the direction of current of each bridge. Output state is as follows. P M 0 1 SINK SOURCE SOURCE SINK
PWM_MODE_1/PWM_MODE_2 Set current decay mode in bridge1 and 2. (See page 8 for details about each mode.) 0 FAST DECAY 1 SLOW DECAY
()Rohm_Reserve Rohm_Reserve is special mode setting port for inspection at shipment. Especially, if Rohm Reserve [3], [4], [5], [7], [8], [9], [10], [11] is set to H by mistake, malfunction may be caused. Be sure not to set.
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7/16
2010.06 - Rev.A
BD64550EFV
H-bridge Driver Operation This IC has built-in 2-channel H-bridge driver. Each can be used for DC motor drive independently. 1. Current setting Motor output current-limit value can be set according to the equation below. Io=(VREF/10)(1/RNFS) [A] Decide within the range VREF = 0.8V to 3.5V, RNFS = 0.04to 0.35. 2. DECAY mode Current decay mode can be selected from serial input at the time of motor chopping drive. Each mode and timing is as follows. SLOW DECAY mode
VM ONOFF OFFOFF ONOFF
Technical Note
FAST DECAY Mode
VM
Timing chart
OFFOFF
FBASE (Internal 8 MHz) Limit value Output current
0
1
48
OFFOFF
ONO
OFFOFF
ONOFF
On time Off time (Set by off time)
SLOW At the time on At the time off (at DECAY) At the time on At the time off (at DECAY) FAST
Fig.16 On/Off Timing at SLOW 3.
Fig.17 On/Off Timing at FAST
Fig.18 DECAY Mode Timing Chart
Protection area for output current value wrong detection In order to avoid wrong detection of current detection comparator by varistor current element in each motor, current detection are masked at the timing as follows. PHASE switching time ENABLE on time When output is on after OFF_TIME is finished at the time of current chopping drive PHASE switching time
PHASE signal Motor current
Mask area BLANK TIME
Fig.19 Timing Chart of PHASE Switching Time ENABLE on time Current chopping driving time
ENABLE Motor current
RNF voltage
Mask area Mask area BLANK TIME BLANK TIME OFF TIME
Fig.20 Timing Chart of ENABLE On Timing
Fig.21 Timing Chart of Current Chopping Driving Time
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2010.06 - Rev.A
BD64550EFV
Technical Note
Switching regulator operation Basic operation A switching regulator circuit that repeats on/off being synchronized with internal CLK (200 KHz) is built-in. The start up output voltage SWOUT (pin 12) becomes up and run step by step with soft start at the VM power-on (VMVMPORH).The output voltage is determined by the equation below with external resistance. VOUTDCDC=VBIAS (R1+R2)/R2 [V] The setting should be performed so that the switching regulator output voltage (VOUTDCDC) waveform is optimized within the range of VOUTDCDC = 3V to 5V, VBIAS = 0.9V (Typ.), R1 + R2 = 1k to 10k, C1 = 1,000pF to 10,000pF.
200KHzCLK
DSEN SWOUT VOUTDCDC
+ +
DRIVER
R1 C1
0.9V BIAS DAC
SWOFF
DSEN R2
SS COUNTER
CLK=1.95kHz
Fig.22 Switching Regulator Block Diagram
Reference clock 200kHz
DUTY MAX
Output voltage MAX_DUTY 92%
SWOUT
Fig.23 Timing Chart of Switching Regulator Operation
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2010.06 - Rev.A
BD64550EFV
Technical Note
Soft start As shown in Fig.24, VOUTDCDC output voltage becomes up and run step by step with soft start at the time of power-on.
VM voltage VMPORH
CLK195 (Internal)
Oscillation
Counter output
1 2 3 4 5 49 63 64
SWOUT
~Duty increase~
Constant ON Duty ON Duty= VDCOUT/VM 1.21V 0.90V 0V 5.0Vor3.3V
DAC output
VOUTDCDC output voltage 0V T1=23.6[msec] T2=32.8[msec]
Fig.24 Soft Starting Time Timing Chart This soft start method is realized by changing comparator positive side voltage that determines output duty of switching regulator to linear using DAC. Soft start time T1 is constant value regardless of VM voltage. Soft start time T1=23.6msec(typ.) Count finish time T2=32.8msec(typ.)
Series regulator operation Inputting switching regulator output into RIN pin (pin 16) enables to drive series regulator circuit. At the time of power-on, output voltage start up step by step with soft starting at the same timing as switching regulator circuit.^Soft start time is 23.6ms (Typ.). Regarding external capacitor of ROUT pin (pin 14), it works normally without setting. But switching noise of switching regulator becomes easy to get in due to dragging on board pattern and the like. Pay attention to switching noise.
RIN Switching regulator Regulator 0.9V ROUT
20k (typ.) Internal CLK 1.95kHz SS COUNTER DAC 30k (typ.)
Fig.25 Series Regulator Block Diagram
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10/16
2010.06 - Rev.A
BD64550EFV
Protection function Protection circuit function Overall DC motor drive circuit Switching regulator circuit Series regulator circuit Overcurrent protection
Technical Note
Overheating protection Overcurrent protection, output overvoltage protection, output low voltage protection None
Operation at protection circuit operation Overheating protectionAll functions are shutout along with junction temperature rise Thermal shutdown temperature 175(typ.)
Switching regulator At protection operation OFF
Series regulator OFF
DC motor OFF
RESET L
Re-start Again power-on
Overcurrent protection (Switching regulator) Set current ISWOC 2.6(A) Switching regulator Operating OFF
Mask time 0.5sec
()
State after operation All function shutout DC motor OFF RESET L Re-start Again power-on
Series regulator OFF
Overcurrent protection (DC motor) Set current IDCOC 3.8(A) Switching regulator ON
Mask time 1.5sec Series regulator ON
State after operation Shown below DC motor OFF RESET L_PULSE Re-start Serial re-input
Operating
Motor current
IDCOC setting value
RESET signal
L
Serial data
Data default
1.5sec
40msec
Fig.26 Timing Chart of Motor Overcurrent Protection
() If the output pulse of switching regulator is 0.5s or below, the overcurrent function does not operate even at the time of overcurrent outflow.
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BD64550EFV
Technical Note
Low voltage protection/overvoltage protection circuit All functions are shutout on the condition of setting value (+30%, -30%) while DSEN pin voltage (pin 18) of switching regulator circuit is monitored.
Set voltage Mask time State after operation
VSWLV VSWOH
0.60(V) 1.20(V)
10sec 10sec
All function shutout All function shutout
Note that output overvoltage and output low voltage protection does not work until soft start count finish (32.8 ms, Typ.) at the time of start up of DC/DC power after power-on. Switching regulator Operating OFF Series regulator OFF DC motor OFF RESET L Re-start Again power-on
DSEN DRIVER 0.9V BIAS DAC SS COUNTER All function off circuit
SWOUT
DSEN
0.60V 1.21V
Mask during soft starting
Fig.27 Switching Regulator Block Diagram RESET function Power-on RESET circuit is built-in for VM power source. H is output at RESET pin through DELAY time of internal counter when power voltage goes up to VMPORH (6.5 V, Typ.) or higher at the time of power-on. In addition, hysteresis is set up at the time of power-down to output L at RESET pin with VMPORL (6.1 V, Typ.) And no response time (2.5s, Typ.) of voltage detection is set in order to avoid wrong detection by sudden power-off.If protection circuits other than overcurrent protection of motor starts operating, RESET is not released if VM power is not on again.
VM
Internal regulator B.G OSC RESET1 VM VM UVLO BG Protection detection other than DCOC RESET1 POWER monitor BG Latch circuit SWOFF SS Counter SOFT START
DCOC RESET2
DCOC Counter
RESET
AND
POR Counter OSC
AND
Fig.28 RESET Internal Circuit Block Diagram
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2010.06 - Rev.A
BD64550EFV
I/O Circuit Diagram OUT1P, OUT1M, OUT2P, OUT2M, RNF1 and RNF2
VM1, VM2
Technical Note
RNF1S and RNF2S
OUT1P, OUT2P
OUT1M, OUT2M
RNF1S, RNF2S
Overcurrent protection circuit
15A(TYP.)
RNF1, RNF2
SWOUT
VM4
RIN and ROUT
RIN
ROUT
SWOUT
DSEN
DSEN
VREF1 and VREF2
Logic input
RESET
RESET
Fig.29 I/O Circuit
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2010.06 - Rev.A
BD64550EFV
Technical Note
Power Dissipation Reduction On the backside of HTSSOP-B40 package, metal is filled in. Heat dissipation is possible by letting in a through hole from backside. Power dissipation can be improved by providing heat dissipation pattern of copper foil or the like not only on the board surface but also on the backside. The metal on the backside shorts with the backside of IC tip and the potential is GND. Therefore, avoid shorts with other potential than GND, or malfunction or destruction may happen. It is recommended that backside metal should short with GND by soldering.
5.0 4.5 4.0
Measuring instrument: TH156 (Kuwano Denki) Measuring state: ROHM substrate mounted Board size:70mmx70mmx1.6mm(Thermal via on the board) Solder the board and exposed heat release part of package backside. Board:1-layer board (Backside copper foil area: 0 mm x 0 mm) Board:2-layer board (Backside copper foil area: 15 mm x 15 mm) Board:2-layer board (Backside copper foil area: 15 mm x 15 mm) Board:4-layer board (Backside copper foil area: 70 mm x 70 mm) Board:ja=78.1/W Board:ja= 64.1/W Board:ja=34.7/W Board:ja=26.6/W
4.7W
3.6W Power Dissipation Pd W)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75
1.95W 1.6W
100
125
150
175
Ambient Temperature : Ta()
Fig.30 Power Dissipation Reduction
Notes for Use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) Connecting the power supply connector backward Connecting the power supply connector backwards may result in damage to the IC. Insert external diodes between the power supply and the IC's power supply pins as well as the motor coil to protect against damage from backward connections. 3) Power supply lines As return of current regenerated by back EMF of motor happens, take steps such as putting capacitor between power supply and GND as a electric pathway for the regenerated current. Be sure that there is no problem with each property such as emptied capacity at lower temperature regarding electrolytic capacitor to decide capacity value. If the connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp diode between the power supply and GND pins. 4) GND potential Ensure a minimum GND pin potential in all operating conditions.
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BD64550EFV
Technical Note
5) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. BD64550EFV expose its frame of the backside of package. Note that this part is assumed to use after providing heat dissipation treatment to improve heat dissipation efficiency . Try to occupy as wide as possible with heat dissipation pattern not only on the board surface but also the backside. 6) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 7) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 8) ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 9) Thermal shutdown circuit The IC has a built-in thermal shutdown circuit (TSD circuit). If the chip temperature becomes Tjmax=150, and higher, coil output to the motor and regulator output will be OFF, and reset output will be L. The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect or indemnify peripheral equipment. Do not use the TSD function to protect peripheral equipment. 10) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 11) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in Fig. 31, the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (P substrate) voltage to input pins.
Resistor Pin A Pin A
P+ N P P+ N P+ N
Tr Pin B
C B E B P P+ N C E
Pin B
N
N
P substrate Parasitic element
GND
Parasitic element
P substrate
GND
Parasitic element
GND
Parasitic element Fig.31 example of IC structure
GND
Other adjacent elements
12) Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either.
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15/16
2010.06 - Rev.A
BD64550EFV
Ordering Part Number
Technical Note
B
D
6
Part No.
4
5
5
0
E
F
V
-
E
2
Part No.
Package EFV : HTSSOP-B40
Packaging and forming specification E2: Embossed tape and reel
HTSSOP-B40
13.60.1 (MAX 13.95 include BURR) (8.4)
40 21

4 +6 -4
Tape Quantity
Embossed carrier tape (with dry pack) 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
0.5 0.15
1.2 0.2
7.80.2
5.40.1
1
0.625
1PIN MARK
20
(3.2)
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
+0.05 0.17 -0.03 S
1.0Max.
0.850.05 0.080.05
+0.05 0.24 -0.04 0.65 0.08 S
0.08
M
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
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16/16
2010.06 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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R1010A

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